Differential data buses are commonly used for relaying data between digital signal processing circuits, and the data is relayed in the form of a digital signal. Differential data buses are shared by many digital signal processing circuits which may operate at different common mode voltage levels, and thus standards are imposed which regulate the minimum and maximum common mode voltages which are permitted on the data bus. However, such standards permit common mode voltage levels within relatively wide voltage ranges. For example, the RS485 standard permits common mode voltage levels of differential signals to range from −7 volts to +12 volts. Digital signal processing circuits are provided with input stages for receiving a differential signal from a differential data bus, which condition the differential signal prior to it being applied to the digital signal processing circuit. Such input stages may operate with supply voltages, and in turn working voltage ranges as low as five volts and even lower. In order to protect such input stages and the digital signal processing circuits from differential signals the common mode voltage of which is outside the working voltage range of the input stage, voltage level shifting circuits are provided. Such voltage level shifting circuits receive the differential signal from the differential data bus, and shift the common mode voltage of the differential signal to a level within the working range of the input stage of the digital signal processing circuit, which is then applied to the input stage.
Typically, such voltage level shifting circuits comprise first and second input terminals for receiving respective first and second signals of a differential signal pair of a differential signal from the differential data bus. First and second resistive voltage divider circuits extend between a voltage reference terminal and the respective first and second input terminals, and define respective first and second output taps intermediate the voltage reference terminal and the first and second input terminals. First and second signals of a level shifted differential signal pair of the level shifted differential signal with the common mode voltage referenced to a voltage reference applied to the voltage reference terminal are produced on the first and second output taps. The level shifted differential signal on the first and second output taps is applied to respective first and second differential inputs of a differential input buffer circuit of the input stage for conditioning prior to being applied to the digital signal processing circuit.
However, such arrangements of voltage level shifting circuits and differential input buffer circuits result in propagation delays when the level shifted differential signal is applied to the differential input buffer circuit, where the differential input buffer circuit includes intrinsic input capacitance. This is particularly so in differential input buffer circuits which are implemented in BiCMOS processes. In general, in such BiCMOS differential input buffer circuits the first and second differential inputs thereof to which the level shifted differential signal is applied each have intrinsic input capacitance through which the differential inputs are capacitively coupled to ground. The propagation delays result from the interaction of the first and second resistive voltage divider circuits of the voltage level shifting circuit with the corresponding intrinsic input capacitance of the first and second differential inputs of the differential input buffer circuit. The interaction of the first and second resistive voltage divider circuits with the corresponding intrinsic input capacitance of the first and second differential inputs of the differential input buffer circuit creates respective low pass filters which cause the propagation delays.
In order to comply with minimum bus loading requirements of data bus standards, and to provide appropriate resistive ratios in the first and second resistive voltage divider circuits, in general, the resistance values of the first and second resistive voltage divider circuits are relatively high, and are of values such that the interaction of the first and second resistive voltage divider circuits with the respective first and second intrinsic input capacitance results in significant propagation delays in the level shifted signal applied to the first and second differential inputs of the differential input buffer circuit. The propagation delay of concern in the level shifted signal applied to the differential input buffer circuit is the time delay from the change in polarity of the differential signal applied to the first and second input terminals of the voltage level shifting circuit to the time a corresponding polarity change occurs in the level shifted differential signal applied to the first and second differential inputs of the differential input buffer circuit. In some cases, as will be discussed in detail below, the propagation delay in the level shifted differential signal resulting from the interaction of the first and second resistive voltage divider circuits with the respective first and second intrinsic input capacitance can be as high as 30 nanoseconds and even higher. While such propagation delays may be tolerated where differential signals are at data rates up to 5 Mbits per second, such propagation delays cannot be tolerated at higher data rates, and in particular, at data rates above 8 Mbits per second. At such data rates propagation delays can lead to corruption and loss of data.
There is therefore a need for a voltage level shifting circuit which addresses the problem of propagation delays. There is also a need for a differential input stage circuit for receiving differential signals from a high swing common mode voltage level differential data bus for applying to a digital signal processing circuit, which addresses the problem of propagation delays. Additionally, there is a need for a method for level shifting a differential signal from a high swing common mode voltage level differential data bus and for applying the level shifted differential signal to a differential input buffer circuit with intrinsic input capacitance which addresses the problem of propagation delays.
The present invention is directed towards providing such a voltage level shifting circuit, a differential input stage circuit and a method for level shifting a differential signal from a differential data bus with high swing common mode voltage levels for applying to a differential input buffer circuit with intrinsic input capacitance.